The present invention generally relates to digital-analog converters and analog-digital converters, and more particularly to a tri-level digital-analog converter and an analog-digital converter such as an oversampling analog-digital converter having a tri-level digital-analog converter.
Presently, much attention is directed to the oversampling analog-digital (A/D) converter. The oversampling A/D converter uses a sampling frequency which is several tens to several hundred times a band which is finally required for a converted signal. As a result, there are the following advantages in using the oversampling A/D converter.
First, it is possible to reduce the order of an analog filter which is provided at an input stage of the A/D converter for the purpose of preventing aliasing noise from mixing into the signal when carrying out the A/D conversion. Second, because it is possible to obtain a high resolution without the use of a highprecision digital-analog (D/A) converter, it is possible to use a more general less accurate analog circuit in the D/A converter.
Accordingly, it is possible to reduce the scale of the circuit because the less accurate analog circuit can be used, but on the other hand, the scale of the digital circuit increases. However, due to the recent progress in integration techniques, the digital circuit can be formed into an integrated circuit with ease even when the scale of the digital circuit is relatively large. For this reason, it is expected that the oversampling A/D converter will be used more
In the oversampling A/D converter, there is a demand po increase the number of bits of the D/A converter which is provided in the A/D converter, so as to improve the signal-to-noise (S/N) ratio of the oversampling A/D converter and realize a stable operation of the oversampling A/D converter.
FIG.1 shows an example of a conventional oversampling A/D converter. A differential circuit 10 obtains a difference between an analog input signal Va and an analog input signal Vd which is output from a D/A converter 15 and corresponds to a previous sampling point. The analog input signal Va is sampled at a sampling frequency fs and supplied to the adder -0. An integrating circuit 11 integrates an output signal of the differential circuit 11, and a comparator 12 compares an output signal of the integrating circuit 11 with a predetermined threshold value. The comparator 12 outputs a digital signal having a "+1" or "-1" level depending on whether the output signal of the integrating circuit 11 has a value greater than or less than the predetermined threshold value. The density of the "+1" level portion and the "-1" level portion of the digital signal output from the comparator 12 changes depending on the analog input signal waveforms.
A delay circuit 14 delays the output digital signal of the comparator 12 by one clock (or one sample), and the D/A converter 15 converts the delayed signal from the delay circuit 14. The D/A converter 15 is of a two-level output type, and converts the delayed signal into an analog signal Vp which corresponds to the "+1" level or an analog signal Vn which corresponds to the "-1" level. An output signal of the D/A converter is supplied to the differential circuit 10 as the analog input signal Vd which corresponds to the previous sampling point.
A digital filter 13 passes the output digital signal of the comparator 12 so as to convert the original analog input signal Va into a digital signal. For example, a lowpass filter is used for the digital filter 13.
In order to improve the resolution of this conventional oversampling A/D converter, it is conceivable to (i) increase the sampling frequency, (ii) increase the order of the integrating circuit 11 to two or greater, or (iii) increase the number of bits of the D/A converter 15.
According to the methods (i) and (ii), it is possible to improve the resolution by using a sigma-delta modulator for the integrating circuit 11 and increasing the order of the modulator from one to two as shown in FIG.2. In FIG.2, the integrating circuit 11 is made up of a second order modulator which includes an adder lla and integrators 11b and 11c, where Z.sup.-1 = 1/fs. However, when the order of the modulator is increased, the integrator shown in FIG. 2 saturates when the quantization error is large, and it becomes necessary to use a D/A converter having a large number of bits as the D/A converter 15 in order to stabilize the operation of the oversampling A/D converter.
On the other hand, according to the method (iii), majority of the D/A converters are of the 1-bit output type, and increasing the number of bits of the D/A converter 15 would mean using a 2-bit output type D/A converter, for example. However, the linearity of the 2-bit output type D/A converter is poor compared to that of the 1-bit output type D/A converter.
In other words, in the case of the 1-bit output type (two-level) D/A converter which outputs the "+1" or "-1" level, no intermediate value exists between the "+1" and "-1" levels and no non-linearity exists between the output values in principle. Hence, as indicated by a phantom line in FIG.3, for example, only a D.C. offset occurs. However, this D.C. offset does not introduce a problem because the effects of the D.C. offset can be eliminated in the digital filter 13 which is provided in a latter stage.
On the other hand, in the case of the 2-bit output type (tri-level) D/A converter which outputs the "+1", "0" or "-1" level, the intermediate value "0" exists. For this reason, no D.C. offset occurs but the linearity becomes poor as indicated by a one-dot chain line in FIG.3, for example.
When the linearity of the output signal of the D/A converter 15 becomes poor, undesired harmonics are introduced in the output of the digital filter 13. As a result, the S/N ratio of the oversampling A/D converter deteriorates. There is therefore a demand to suppress the non-linearity of the output of the tri-level D/A converter which is used in the oversampling A/D converter and improve the linearity of the output characteristic of the tri-level D/A converter.